58 search results - page 11 / 12 » Verifying Concurrent Systems with Symbolic Execution |
DSD
2004
IEEE
14 years 1 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
TABLEAUX
1998
Springer
14 years 2 months ago
1998
Springer
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
POPL
2011
ACM
13 years 19 days ago
2011
ACM
We consider programs for embedded real-time systems which use priority-driven preemptive scheduling with task priorities adjusted dynamically according to the immediate ceiling pr...
CORR
2010
Springer
13 years 10 months ago
2010
Springer
Message Sequence Charts (MSCs) are an appealing visual formalism mainly used in the early stages of system design to capture the system requirements. However, if we move towards a...
SIGSOFT
2007
ACM
14 years 10 months ago
2007
ACM
Asynchronous systems components are hard to write, hard to reason about, and (not coincidentally) hard to mechanically verify. In order to achieve high performance, asynchronous c...