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» Verifying Controlled Components
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HVC
2007
Springer
103views Hardware» more  HVC 2007»
14 years 3 months ago
Verifying Parametrised Hardware Designs Via Counter Automata
The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of suc...
Ales Smrcka, Tomás Vojnar
CBSE
2011
Springer
12 years 8 months ago
Automating information flow control in component-based distributed systems
Automating the construction of secure distributed systems becomes necessary. Indeed, developing security code requires a deep expertise and verifying that the developed code respe...
Takoua Abdellatif, Lilia Sfaxi, Riadh Robbana, Yas...
ECAI
2006
Springer
14 years 14 days ago
Verifying Interlevel Relations Within Multi-Agent Systems
An approach to handle the complex dynamics of a multi-agent system is based on distinguishing aggregation levels by structuring the system into parts or components. The behavior of...
Alexei Sharpanskykh, Jan Treur
DAC
1990
ACM
14 years 26 days ago
Timing Verification Using HDTV
In this paper, we provide an overview of a system designed for verifying the consistency of timing specifications for digital circuits. The utility of the system comes from the ne...
Alan R. Martello, Steven P. Levitan, Donald M. Chi...
CBSE
2006
Springer
14 years 16 days ago
A Component Model Engineered with Components and Aspects
This paper presents AOKell, a framework for engineering component-based systems. This framework implements the Fractal model, a hierarchical and dynamic component model. The novelt...
Lionel Seinturier, Nicolas Pessemier, Laurence Duc...