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» Verifying Progress in Timed Systems
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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 3 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
DIALM
2003
ACM
99views Algorithms» more  DIALM 2003»
14 years 3 months ago
Spatio-temporal data reduction with deterministic error bounds
A common way of storing spatio-temporal information about mobile devices is in the form of a 3D (2D geography + time) trajectory. We argue that when cellular phones and Personal D...
Hu Cao, Ouri Wolfson, Goce Trajcevski
UIST
2000
ACM
14 years 2 months ago
Fluid sketches: continuous recognition and morphing of simple hand-drawn shapes
We describe a new sketching interface in which shape recognition and morphing are tightly coupled. Raw input strokes are continuously morphed into ideal geometric shapes, even bef...
James Arvo, Kevin Novins
RSP
1999
IEEE
122views Control Systems» more  RSP 1999»
14 years 2 months ago
Incremental Compilation for Logic Emulation
Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic...
Russell Tessier
LCPC
2009
Springer
14 years 2 months ago
Enforcing Textual Alignment of Collectives Using Dynamic Checks
Abstract. Many parallel programs are written in a single-program, multipledata (SPMD) style, in which synchronization is provided using collective operations that all threads execu...
Amir Kamil, Katherine A. Yelick