Incremental Compilation for Logic Emulation

Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic gates. While software support for translating new user designs from gate and RTL-level netlists to FPGA bitstreams has improved steadily, little work has been done in developing techniques to support the translation of incremental design changes at the netlist level to a set of replacement bitstreams for a small number of FPGAs in a multi-FPGA system. As system sizes and design compilation times increase, the need to support rapid, incremental compilation grows progressively important. In this paper we describe and analyze a set of incremental compilation steps, including incremental design partitioning and incremental inter-FPGA routing, for two specific classes of multi-FPGA emulation systems. These classes are defined by the techniques that emulation software systems use to determine inter-FPGA communicat...

• Type: Conference
• Year: 1999
• Where: RSP
• Authors: Russell Tessier
• Keywords: Control Systems, Incremental, Incremental Compilation, Incremental Design, RSP 1999