1093 search results - page 117 / 219 » Verifying VLSI Circuits |
ICCAD
1995
IEEE
14 years 15 days ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...
JIRS
2007
13 years 8 months ago
2007
A detailed step-by-step approach is presented to optimize, standardize, and automate the process of unmanned vehicle controller design, evaluation, validation and verification, fol...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—Future computing systems will feature many cores that run fast, but might show more faults compared to existing CMOS technologies. New software methodologies must be adopted to ...
VLSID
2008
IEEE
14 years 9 months ago
2008
IEEE
Negative Bias Temperature Instability (NBTI) has been identified as a major and critical reliability issue for PMOS devices in nano-scale designs. It manifests as a negative thres...