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» Verifying VLSI Circuits
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VLSI
2010
Springer
13 years 7 months ago
Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...
Eliyah Kilada, Shomit Das, Kenneth S. Stevens
VLSID
2010
IEEE
190views VLSI» more  VLSID 2010»
13 years 7 months ago
Rethinking Threshold Voltage Assignment in 3D Multicore Designs
Due to the inherent nature of heat flow in 3D integrated circuits, stacked dies exhibit a wide range of thermal characteristics. The strong dependence of leakage with temperature...
Koushik Chakraborty, Sanghamitra Roy
VLSI
2010
Springer
13 years 3 months ago
Spatial EM jamming: A countermeasure against EM Analysis?
Electro-Magnetic Analysis has been identified as an efficient technique to retrieve the secret key of cryptographic algorithms. Although similar mathematically speaking, Power or E...
Francois Poucheret, Lyonel Barthe, Pascal Benoit, ...
VLSID
2007
IEEE
160views VLSI» more  VLSID 2007»
14 years 9 months ago
Spectral RTL Test Generation for Microprocessors
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
Nitin Yogi, Vishwani D. Agrawal
VLSID
2007
IEEE
108views VLSI» more  VLSID 2007»
14 years 9 months ago
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vai...