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» Verifying VLSI Circuits
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GLVLSI
2006
IEEE
110views VLSI» more  GLVLSI 2006»
14 years 2 months ago
Synthesis of a wideband low noise amplifier
Two generations of a wideband low noise amplifier (LNA) employing noise canceling principle have been synthesized. The first generation design was fabricated in a 0.35 µm SiGe Bi...
Abhishek Jajoo, Michael Sperling, Tamal Mukherjee
GLVLSI
2006
IEEE
113views VLSI» more  GLVLSI 2006»
14 years 2 months ago
Statistical gate delay calculation with crosstalk alignment consideration
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
Andrew B. Kahng, Bao Liu, Xu Xu
GLVLSI
2006
IEEE
90views VLSI» more  GLVLSI 2006»
14 years 2 months ago
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
Chang Woo Kang, Massoud Pedram
GLVLSI
2006
IEEE
185views VLSI» more  GLVLSI 2006»
14 years 2 months ago
Application of fast SOCP based statistical sizing in the microprocessor design flow
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
Murari Mani, Mahesh Sharma, Michael Orshansky
GLVLSI
2006
IEEE
142views VLSI» more  GLVLSI 2006»
14 years 2 months ago
Dynamic instruction schedulers in a 3-dimensional integration technology
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...
Kiran Puttaswamy, Gabriel H. Loh