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» Verifying VLSI Circuits
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ATS
2010
IEEE
253views Hardware» more  ATS 2010»
13 years 6 months ago
On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation
One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and o...
Xiao Liu, Qiang Xu
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 5 months ago
Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
14 years 2 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
ISPD
2005
ACM
151views Hardware» more  ISPD 2005»
14 years 2 months ago
Thermal via placement in 3D ICs
As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promi...
Brent Goplen, Sachin S. Sapatnekar
SBCCI
2009
ACM
131views VLSI» more  SBCCI 2009»
14 years 1 months ago
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown
Because of the aggressive scaling of integrated circuits and the given limits of atomic scales, circuit designers have to become more and more aware of the arising reliability and...
Hagen Sämrow, Claas Cornelius, Frank Sill, An...