1093 search results - page 59 / 219 » Verifying VLSI Circuits |
VLSID
2000
IEEE
14 years 2 months ago
2000
IEEE
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
DFT
1998
IEEE
14 years 2 months ago
1998
IEEE
The statistical variations in electrical parameters, such as transistor gain factors and interconnect resistances, due to variations in the manufacturing process are studied using...
DFT
1997
IEEE
14 years 2 months ago
1997
IEEE
The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evalua...
VLSI
2010
Springer
13 years 4 months ago
2010
Springer
Although local biasing of components used in an analog circuit is shown to be a very attractive design methodology, significantly simplifying the design procedure [3], it makes the...
GLVLSI
2006
IEEE
14 years 4 months ago
2006
IEEE
Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog ...