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» Verifying VLSI Circuits

23

GLVLSI
1998
IEEE

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IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits

13 years 11 months ago

IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits

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Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy

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33

DFT
1993
IEEE

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Neural Networks for Multiple Fault Diagnosis in Analog Circuits

13 years 11 months ago

Neural Networks for Multiple Fault Diagnosis in Analog Circuits

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Alessandra Fanni, Alessandro Giua, Enrico Sandoli

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22

GLVLSI
1995
IEEE

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A new look at the conditions for the synthesis of speed-independent circuits

13 years 11 months ago

A new look at the conditions for the synthesis of speed-independent circuits

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Enric Pastor, Jordi Cortadella, Oriol Roig

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23

VLSID
2002
IEEE

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Register Transfer Operation Analysis during Data Path Verification

14 years 7 months ago

Register Transfer Operation Analysis during Data Path Verification

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A control part ? data path partition based sequential circuit verification scheme aimed at avoiding state explosion comprises two major modules namely, a data path verifier and a ...

D. Sarkar

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20

GLVLSI
2006
IEEE

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Leakage current starved domino logic

14 years 1 months ago

Leakage current starved domino logic

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A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...

Zhiyu Liu, Volkan Kursun

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