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» Verifying a Simple Pipelined Microprocessor Using Maude
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DSN
2004
IEEE
13 years 11 months ago
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and protecting against single-event upsets in digital...
Nicholas J. Wang, Justin Quek, Todd M. Rafacz, San...
ENTCS
2007
88views more  ENTCS 2007»
13 years 7 months ago
Mothers of Pipelines
We present a method for pipeline verification using SMT solvers. It is based on a non-deterministic “mother pipeline” machine (MOP) that abstracts the instruction set archite...
Sava Krstic, Robert B. Jones, John O'Leary
TCAD
2008
101views more  TCAD 2008»
13 years 7 months ago
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
Functional correctness is a vital attribute of any hardware design. Unfortunately, due to extremely complex architectures, widespread components, such as microprocessors, are often...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
ISCA
1998
IEEE
108views Hardware» more  ISCA 1998»
14 years 4 days ago
Pipeline Gating: Speculation Control for Energy Reduction
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...
Srilatha Manne, Artur Klauser, Dirk Grunwald
IPPS
2006
IEEE
14 years 1 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner