2 search results - page 1 / 1 » Verifying a Synthesized Implementation of IEEE-754 Floating-... |
CJ
2010
13 years 11 months ago
2010
rder logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, ...
DAC
1996
ACM
14 years 3 months ago
1996
ACM
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...