Sciweavers

1886 search results - page 13 / 378
» Verifying and validating a simulation model
Sort
View
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
14 years 1 months ago
Validation of Embedded Systems Using Formal Method Aided Simulation
This paper proposes a validation approach, based on simulation, which addresses problems related to both state space explosion of formal methods and low coverage of informal metho...
Daniel Karlsson, Petru Eles, Zebo Peng
SPIN
2010
Springer
13 years 5 months ago
An Automata-Based Symbolic Approach for Verifying Programs on Relaxed Memory Models
This paper addresses the problem of verifying programs for the relaxed memory models implemented in modern processors. Specifically, it considers the TSO (Total Store Order) relax...
Alexander Linden, Pierre Wolper
DAC
1997
ACM
13 years 11 months ago
Toward Formalizing a Validation Methodology Using Simulation Coverage
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...
Aarti Gupta, Sharad Malik, Pranav Ashar
APSEC
2005
IEEE
14 years 1 months ago
Simulation-based Validation and Defect Localization for Evolving, Semi-Formal Requirements Models
When requirements models are developed in an iterative and evolutionary way, requirements validation becomes a major problem. In order to detect and fix problems early, the speci...
Christian Seybold, Silvio Meier
WSC
1998
13 years 8 months ago
Bootstrapping and Validation of Metamodels in Simulation
Bootstrapping is a resampling technique that requires less computer time than simulation does. Bootstrapping -like simulation-must be defined for each type of application. This pa...
Jack P. C. Kleijnen, A. J. Feelders, Russell C. H....