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» Very Compact FPGA Implementation of the AES Algorithm
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FSE
2008
Springer
166views Cryptology» more  FSE 2008»
13 years 9 months ago
Accelerating the Whirlpool Hash Function Using Parallel Table Lookup and Fast Cyclical Permutation
Hash functions are an important building block in almost all security applications. In the past few years, there have been major advances in the cryptanalysis of hash functions, es...
Yedidya Hilewitz, Yiqun Lisa Yin, Ruby B. Lee
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Design and design automation of rectification logic for engineering change
In a later stage of a VLSI design, it is quite often to modify a design implementation to accommodate the new specification, design errors, or to meet design constraints. In addit...
Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 1 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
IPPS
2006
IEEE
14 years 1 months ago
A multiprocessor architecture for the massively parallel model GCA
The GCA (Global Cellular Automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical...
Wolfgang Heenes, Rolf Hoffmann, Johannes Jendrsczo...
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
14 years 27 days ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna