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» Very Compact FPGA Implementation of the AES Algorithm
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DCC
2002
IEEE
14 years 7 months ago
Optimized Edgebreaker Encoding for Large and Regular Triangle Meshes
We present a technique designed aiming to improve the compression of the Edgebreaker CLERS string for large and regular meshes, where regularity is understood as the compactness o...
Andrzej Szymczak
FCCM
2000
IEEE
131views VLSI» more  FCCM 2000»
13 years 11 months ago
A Reliable LZ Data Compressor on Reconfigurable Coprocessors
Data compression techniques based on Lempel-Ziv (LZ) algorithm are widely used in a variety of applications, especially in data storage and communications. However, since the LZ a...
Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluske...
DATE
2009
IEEE
242views Hardware» more  DATE 2009»
14 years 2 months ago
A high performance reconfigurable Motion Estimation hardware architecture
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and hi...
Ozgur Tasdizen, Halil Kukner, Abdulkadir Akin, Ilk...
ISCA
2007
IEEE
167views Hardware» more  ISCA 2007»
14 years 1 months ago
New cache designs for thwarting software cache-based side channel attacks
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...
Zhenghong Wang, Ruby B. Lee
IWNAS
2008
IEEE
14 years 1 months ago
A Novel Embedded Accelerator for Online Detection of Shrew DDoS Attacks
∗ As one type of stealthy and hard-to-detect attack, lowrate TCP-targeted DDoS attack can seriously throttle the throughput of normal TCP flows for a long time without being noti...
Hao Chen, Yu Chen