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» Very Compact FPGA Implementation of the AES Algorithm
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HOST
2008
IEEE
14 years 1 months ago
Place-and-Route Impact on the Security of DPL Designs in FPGAs
—Straightforward implementations of cryptographic algorithms are known to be vulnerable to attacks aimed not at the mathematical structure of the cipher but rather at the weak po...
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Dange...
LCPC
2005
Springer
14 years 26 days ago
Scalable Array SSA and Array Data Flow Analysis
Static Single Assignment (SSA) has been widely accepted as the intermediate program representation of choice in most modern compilers. It allows for a much more efficient data flo...
Silvius Rus, Guobin He, Lawrence Rauchwerger
TC
2010
13 years 5 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
VISUALIZATION
2000
IEEE
13 years 11 months ago
On-the-Fly rendering of losslessly compressed irregular volume data
Very large irregular-grid data sets are represented as tetrahedral meshes and may incur significant disk I/O access overhead in the rendering process. An effective way to allevia...
Chuan-Kai Yang, Tulika Mitra, Tzi-cker Chiueh
SIGCOMM
2006
ACM
14 years 1 months ago
Beyond bloom filters: from approximate membership checks to approximate state machines
Many networking applications require fast state lookups in a concurrent state machine, which tracks the state of a large number of flows simultaneously. We consider the question ...
Flavio Bonomi, Michael Mitzenmacher, Rina Panigrah...