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» Very Compact FPGA Implementation of the AES Algorithm
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CHES
2007
Springer
327views Cryptology» more  CHES 2007»
14 years 2 months ago
On the Power of Bitslice Implementation on Intel Core2 Processor
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
Mitsuru Matsui, Junko Nakajima
WCE
2007
13 years 9 months ago
Secure Multicarrier Modem on FPGA
— The paper deals with the design and realization of a secure multicarrier modem on FPGA. The crypto-modem principle is adopted. An encryption block is integrated in the modem tr...
Galia Marinova, Vassil Guliashki, Didier Le Ruyet,...
CRYPTO
2011
Springer
237views Cryptology» more  CRYPTO 2011»
12 years 8 months ago
Automatic Search of Attacks on Round-Reduced AES and Applications
In this paper, we describe versatile and powerful algorithms for searching guess-and-determine and meet-in-the-middle attacks on byte-oriented symmetric primitives. To demonstrate ...
Charles Bouillaguet, Patrick Derbez, Pierre-Alain ...
FDTC
2010
Springer
138views Cryptology» more  FDTC 2010»
13 years 6 months ago
A Continuous Fault Countermeasure for AES Providing a Constant Error Detection Rate
Many implementations of cryptographic algorithms have shown to be susceptible to fault attacks. For some of them, countermeasures against specific fault models have been proposed. ...
Marcel Medwed, Jörn-Marc Schmidt
PAIRING
2010
Springer
153views Cryptology» more  PAIRING 2010»
13 years 6 months ago
Compact Hardware for Computing the Tate Pairing over 128-Bit-Security Supersingular Curves
This paper presents a novel method for designing compact yet efficient hardware implementations of the Tate pairing over supersingular curves in small characteristic. Since such cu...
Nicolas Estibals