26 search results - page 4 / 6 » View Caching: Efficient Software Shared Memory for Dynamic C... |
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--Ensuring the correctness of complex implementations of software transactional memory (STM) is a daunting task. Attempts have been made to formally verify STMs, but these ...
PDP
2010
IEEE
14 years 25 days ago
2010
IEEE
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
ICTAC
2010
Springer
13 years 6 months ago
2010
Springer
We consider software verification of imperative programs by theorem proving in higher-order separation logic. Of particular interest are the difficulties of encoding and reasoning ...