This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...
The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) ...
This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit Digital to Analog Converter (DAC) using the JPL stand-alo...
Ricardo Salem Zebulum, Didier Keymeulen, Vu Duong,...
A new asynchronous data transfer scheme using multiple-valued 2-color 1-phase coding, called a bidirectional data transfer scheme, is proposed for a highperformance and low-power ...