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CSREAESA
2003
13 years 9 months ago
Power Optimized Combinational Logic Design
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...
GLVLSI
1999
IEEE
59views VLSI» more  GLVLSI 1999»
13 years 12 months ago
Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain
The inherent bistability and picosecond time-scale switching of the resonant tunneling diode (RTD) provides an ideal element for the design of digital circuits and analog signal q...
T. P. E. Broekaert, B. Brar, F. Morris, A. C. Seab...
ITC
1996
IEEE
107views Hardware» more  ITC 1996»
13 years 11 months ago
Digital Integrated Circuit Testing using Transient Signal Analysis
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
James F. Plusquellic, Donald M. Chiarulli, Steven ...
HPDC
2010
IEEE
13 years 8 months ago
Cluster-wide context switch of virtualized jobs
Clusters are mostly used through Resources Management Systems (RMS) with a static allocation of resources for a bounded amount of time. Those approaches are known to be insufficie...
Fabien Hermenier, Adrien Lebre, Jean-Marc Menaud
BROADNETS
2005
IEEE
14 years 1 months ago
Bandwidth guaranteed multicast scheduling for virtual output queued packet switches
Multicast enables efficient data transmission from one source to multiple destinations, and has been playing an important role in Internet multimedia applications. Although sever...
Deng Pan, Yuanyuan Yang