Power Optimized Combinational Logic Design

In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each gate. A powerful combinational logic optimization method using k-map is presented here that is based on disjoint implicants (implicates) of a function. More than 10% reduction in switching activity has been obtained with marginal increase in circuit area and delay.

• Type: Conference
• Year: 2003
• Where: CSREAESA
• Authors: R. V. Menon, S. Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi
• Keywords: Combinational Circuits, CSREAESA 2003, CSREAESA 2007, Output Nodes, Powerful Combinational Logic