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FPL
2005
Springer
112views Hardware» more  FPL 2005»
14 years 1 months ago
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
Anthony J. Yu, Guy G. Lemieux
ICCD
2000
IEEE
123views Hardware» more  ICCD 2000»
14 years 4 months ago
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating of the ground bounce is presen...
Payam Heydari, Massoud Pedram
DATE
2006
IEEE
176views Hardware» more  DATE 2006»
14 years 1 months ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...
STOC
1998
ACM
96views Algorithms» more  STOC 1998»
13 years 12 months ago
Randomized Protocols for Low Congestion Circuit Routing in Multistage Interconnection Networks
In this paper we study randomized algorithms for circuit switching on multistage networks related to the butterfly. We devise algorithms that route messages by constructing circu...
Richard Cole, Bruce M. Maggs, Friedhelm Meyer auf ...
ASPDAC
2008
ACM
160views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Reconfigurable RTD-based circuit elements of complete logic functionality
Abstract--Resonant tunneling diodes (RTDs) have demonstrated promising circuit characteristics of high speed switching property and versatile functionality with negative differenti...
Yexin Zheng, Chao Huang