1393 search results - page 203 / 279 » Virtual-Channel Flow Control |
132
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EUROMICRO
1999
IEEE
15 years 6 months ago
1999
IEEE
In this paper we present an improved scheduling technique for the synthesis of time-triggered embedded systems. Our system model captures both the flow of data and that of control...
130
Voted
EUROMICRO
1998
IEEE
15 years 6 months ago
1998
IEEE
The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have develop...
114
Voted
IPPS
1998
IEEE
15 years 6 months ago
1998
IEEE
In distributed-memory message-passing architectures reducing communication cost is extremely important. In this paper, we present a technique to optimize communication globally. O...
112
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IPPS
1998
IEEE
15 years 6 months ago
1998
IEEE
An effort to formalize the process of software pipelining loops with conditions is presented in this paper. A formal framework for scheduling such loops, based on representing set...
122
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ICCAD
1992
IEEE
15 years 6 months ago
1992
IEEE
High-level synthesis (HLS) requires more designer interaction to better meet the needs of experienced designers. However, attempts to create a highly interactive synthesis process...