254 search results - page 30 / 51 » Weaving Relations for Cache Performance |
ISCA
1994
IEEE
14 years 2 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
EUC
2006
Springer
14 years 1 months ago
2006
Springer
Mobile devices have difficulty in sustaining various services as in a wired environment, due to the storage shortage of the mobile device. The research[8] which provides remote sto...
OSDI
2008
ACM
14 years 10 months ago
2008
ACM
Conceptually, fast server-side page cache storage could dramatically reduce paging I/O. In this extended abstract, we speculate how such a device might be used, then show how it c...
ASPLOS
2004
ACM
14 years 3 months ago
2004
ACM
Tracing garbage collectors traverse references from live program variables, transitively tracing out the closure of live objects. Memory accesses incurred during tracing are essen...
MICRO
2006
IEEE
14 years 4 months ago
2006
IEEE
Ring interconnects may be an attractive solution for future chip multiprocessors because they can enable faster links than buses and simpler switches than arbitrary switched inter...