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HPCA
2008
IEEE
14 years 10 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
CCGRID
2010
IEEE
13 years 10 months ago
FaReS: Fair Resource Scheduling for VMM-Bypass InfiniBand Devices
In order to address the high performance I/O needs of HPC and enterprise applications, modern interconnection fabrics, such as InfiniBand and more recently, 10GigE, rely on network...
Adit Ranadive, Ada Gavrilovska, Karsten Schwan
EUROGRAPHICS
2010
Eurographics
14 years 6 months ago
Real-time Realistic Ocean Lighting using Seamless Transitions from Geometry to BRDF
Realistic animation and rendering of the ocean is an important aspect for simulators, movies and video games. By nature, the ocean is a difficult problem for Computer Graphics: i...
Eric Bruneton, Fabrice Neyret, Nicolas Holzschuch
IPPS
2006
IEEE
14 years 3 months ago
Reconfigurable communications for image processing applications
: This work tries to reuse programmable communication resources like a Network-on-Chip (NoC) in the acceleration of image applications. We show a mathematical model for the computa...
André Borin Soares, Luigi Carro, Altamiro A...
SC
2005
ACM
14 years 3 months ago
An Application-Based Performance Characterization of the Columbia Supercluster
Columbia is a 10,240-processor supercluster consisting of 20 Altix nodes with 512 processors each, and currently ranked as one of the fastest computers in the world. In this paper...
Rupak Biswas, M. Jahed Djomehri, Robert Hood, Haoq...