174 search results - page 23 / 35 » Web-based Distributed VLSI Design |
VLSID
2005
IEEE
14 years 10 months ago
2005
IEEE
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
VLSID
2005
IEEE
14 years 10 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
ASAP
2006
IEEE
14 years 3 months ago
2006
IEEE
Abstract – The storage requirements in data-dominant signal processing systems, whose behavior is described by arraybased, loop-organized algorithmic specifications, have an imp...
ASPDAC
2007
ACM
14 years 1 months ago
2007
ACM
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Ma...
SIGCSE
2004
ACM
14 years 3 months ago
2004
ACM
Finding just the right example to answer a question can be difficult for CS1 students and teachers. For this to work well there must be an intuitive interface coupled to an approp...