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GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
KI
2007
Springer
14 years 5 months ago
Pinpointing in the Description Logic EL+
Axiom pinpointing has been introduced in description logics (DLs) to help the user understand the reasons why consequences hold by computing minimal subsets of the knowledge base t...
Franz Baader, Rafael Peñaloza, Boontawee Su...
NIPS
2007
14 years 12 days ago
An in-silico Neural Model of Dynamic Routing through Neuronal Coherence
We describe a neurobiologically plausible model to implement dynamic routing using the concept of neuronal communication through neuronal coherence. The model has a three-tier arc...
Devarajan Sridharan, Brian Percival, John V. Arthu...
ICDE
2012
IEEE
199views Database» more  ICDE 2012»
12 years 1 months ago
Physically Independent Stream Merging
—A facility for merging equivalent data streams can support multiple capabilities in a data stream management system (DSMS), such as query-plan switching and high availability. O...
Badrish Chandramouli, David Maier, Jonathan Goldst...
ICCAD
1994
IEEE
114views Hardware» more  ICCAD 1994»
14 years 3 months ago
Performance-driven synthesis of asynchronous controllers
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...
Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas ...