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ICCD
1995
IEEE
83views Hardware» more  ICCD 1995»
13 years 11 months ago
Concurrent timing optimization of latch-based digital systems
Many design techniques have been proposed to optimize the performance of a digital system implemented in a given technology. Each of these techniques can be advantageous in partic...
Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C...
ISCA
1995
IEEE
147views Hardware» more  ISCA 1995»
13 years 11 months ago
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
Alvin R. Lebeck, David A. Wood
ASPDAC
2008
ACM
127views Hardware» more  ASPDAC 2008»
13 years 9 months ago
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distr...
Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-S...
FMICS
2008
Springer
13 years 9 months ago
Dynamic Event-Based Runtime Monitoring of Real-Time and Contextual Properties
Given the intractability of exhaustively verifying software, the use of runtime-verification, to verify single execution paths at runtime, is becoming popular. Although the use of ...
Christian Colombo, Gordon J. Pace, Gerardo Schneid...
IPCO
2010
148views Optimization» more  IPCO 2010»
13 years 9 months ago
Prize-Collecting Steiner Network Problems
In the Steiner Network problem we are given a graph with edge-costs and connectivity requirements between node pairs , . The goal is to find a minimum-cost subgraph of that contain...
MohammadTaghi Hajiaghayi, Rohit Khandekar, Guy Kor...