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ASPDAC
2006
ACM
103views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Low area pipelined circuits by multi-clock cycle paths and clock scheduling
— A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algor...
Bakhtiar Affendi Rosdi, Atsushi Takahashi
MOBIQUITOUS
2005
IEEE
15 years 9 months ago
WebProfiles: A Negotiation Model for User Awareness in Personal Area Networks
Automatic adaptation of the environment to user preferences results in personalized ambients that fulfill user interaction requirements in a more suitable way. However, the proble...
Juan Ignacio Vázquez, Diego López de...
MSS
2003
IEEE
113views Hardware» more  MSS 2003»
15 years 9 months ago
Design and Implementation of Multiple Addresses Parallel Transmission Architecture for Storage Area Network
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...
Bin Meng, Patrick B. T. Khoo, T. C. Chong
DATE
2000
IEEE
75views Hardware» more  DATE 2000»
15 years 8 months ago
Layout Compaction for Yield Optimization via Critical Area Minimization
This paper presents a new compaction algorithm to improve the yield of IC layout. The yield is improved by reducing the area where the faults are more likely to happen known as cr...
Youcef Bourai, C.-J. Richard Shi
DCG
2010
77views more  DCG 2010»
15 years 4 months ago
Oriented Mixed Area and Discrete Minimal Surfaces
Abstract. Recently a curvature theory for polyhedral surfaces has been established which associates with each face a mean curvature value computed from areas and mixed areas of tha...
Christian Müller, Johannes Wallner