Sciweavers

3338 search results - page 27 / 668
» Wireless Systems-on-a-Chip Design
Sort
View
SOCC
2008
IEEE
233views Education» more  SOCC 2008»
14 years 5 months ago
A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards
Abstract— In this paper we present an efficient system-onchip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable datapa...
Yang Sun, Joseph R. Cavallaro
ISCAS
2005
IEEE
190views Hardware» more  ISCAS 2005»
14 years 4 months ago
Digital VLSI OFDM transceiver architecture for wireless SoC design
—This paper presents the VLSI architecture of an OFDM baseband transceiver for wireless communications. The open-/closed-loop carrier recovery achieves the stepping frequency acq...
Wei-Hsiang Tseng, Ching-Chi Chang, Chorng-Kuang Wa...
ADHOC
2011
13 years 2 months ago
RadiaLE: A framework for designing and assessing link quality estimators in wireless sensor networks
—Stringent cost and energy constraints impose the use of low-cost and low-power radio transceivers in large-scale wireless sensor networks (WSNs). This fact, together with the ha...
Nouha Baccour, Anis Koubaa, Maissa Ben Jamâa...
SASO
2008
IEEE
14 years 5 months ago
Aspects of Distance Sensitive Design of Wireless Sensor Networks
—Distance sensitivity is a locality concept that is useful for designing scalable wireless sensor network applications. In this paper, we formally define distance sensitivity an...
Vinod Kulathumani, Anish Arora
ICC
2007
IEEE
130views Communications» more  ICC 2007»
14 years 5 months ago
Queuing with Adaptive Modulation over MIMO Wireless Links for Deadline Constrained Traffic: Cross-Layer Analysis and Design
In this paper, we consider a deadline constrained traffic and analyze the joint effects of packet queuing and adaptive modulation (AM) for packet transmission in MIMO systems. We p...
Jalil S. Harsini, Farshad Lahouti