564 search results - page 110 / 113 » Wireplanning in logic synthesis |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
CODES
2008
IEEE
14 years 1 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Architectural advances of modern systems has often been at odds with control complexity, requiring significant effort in both design and verification. This is particularly true ...
ASPDAC
2005
ACM
14 years 27 days ago
2005
ACM
The progressive trend of fabrication technologies towards the nanometer regime has created a number of new physical design challenges for computer architects. Design complexity, u...
HT
2004
ACM
14 years 23 days ago
2004
ACM
In this paper, we present a model-driven methodology and toolset for automatic generation of hypertext system repositories. Our code generator, called Bamboo, is based on a Contai...