564 search results - page 33 / 113 » Wireplanning in logic synthesis |
ISQED
2011
IEEE
13 years 4 days ago
2011
IEEE
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
A special logic synthesis problem is considered for Boolean functions which have large don’t care sets and are irregular. Here, a function is considered as irregular if the inpu...
CADE
2002
Springer
14 years 8 months ago
2002
Springer
TABLEAUX
2009
Springer
14 years 3 months ago
2009
Springer
This paper presents a method for synthesising sound and complete tableau calculi. Given a specification of the formal semantics of a logic, the method generates a set of tableau i...
TVLSI
1998
13 years 8 months ago
1998
— Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of hig...