564 search results - page 3 / 113 » Wireplanning in logic synthesis |
TCAD
2008
13 years 6 months ago
2008
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
As CMOS devices are scaled down into the nanometer regime, concerns about reliability are mounting. Instead of viewing nanoscale characteristics as an impediment, technologies suc...
TODAES
2002
13 years 7 months ago
2002
CORR
2010
Springer
13 years 5 months ago
2010
Springer
– This paper addresses the problem of forbidden states of non safe Petri Net (PN) modelling discrete events systems. To prevent the forbidden states, it is possible to use condit...
TODAES
2010
13 years 5 months ago
2010
