564 search results - page 49 / 113 » Wireplanning in logic synthesis |
CBSE
2005
Springer
14 years 2 months ago
2005
Springer
We consider a class of component-based software models with interaction style of buffered asynchronous message passing between components with ports, represented by UML-RT. After ...
AC
2003
Springer
14 years 1 months ago
2003
Springer
Abstract. As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call...
ICCAD
1992
IEEE
14 years 17 days ago
1992
IEEE
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
EURODAC
1994
IEEE
14 years 19 days ago
1994
IEEE
An approach for stuck-at-i and delay-fault testing of redundant circuits without modifying the logic is proposed. The only requirement is the ability to control both phases of eac...
MSE
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short co...