564 search results - page 4 / 113 » Wireplanning in logic synthesis |
DAC
2000
ACM
13 years 11 months ago
2000
ACM
In many modern designs, timing is either a key optimization goal and/or a mandatory constraint. We propose the first intellectual property protection technique using watermarking ...
DAC
2012
ACM
11 years 9 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
OOPSLA
2010
Springer
13 years 5 months ago
2010
Springer
Given a high-level specification and a low-level programming language, our goal is to automatically synthesize an efficient program that meets the specification. In this paper,...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— The research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. Hence synthesis of reversible logic...
DAC
2012
ACM
11 years 9 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...