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» Wireplanning in logic synthesis
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CHES
2005
Springer
82views Cryptology» more  CHES 2005»
14 years 27 days ago
Masking at Gate Level in the Presence of Glitches
Abstract. It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by “secure” random masking schemes, leak side-cha...
Wieland Fischer, Berndt M. Gammel
LCN
2003
IEEE
14 years 19 days ago
An Optoelectronic Multi-Terabit CMOS Switch Core for Local Area Networks
Optoelectronic integrated circuits can support thousands of integrated optical laser diodes and photodetectors bonded to a high-performance CMOS substrate, and can be used in the ...
Honglin Wu, Amir Gourgy, Ted H. Szymanski
ASPDAC
2007
ACM
124views Hardware» more  ASPDAC 2007»
13 years 11 months ago
BddCut: Towards Scalable Symbolic Cut Enumeration
While the covering algorithm has been perfected recently by the iterative approaches, such as DAOmap and IMap, its application has been limited to technology mapping. The main fact...
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
ICCAD
2007
IEEE
151views Hardware» more  ICCAD 2007»
13 years 11 months ago
A design flow dedicated to multi-mode architectures for DSP applications
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
Cyrille Chavet, Caaliph Andriamisaina, Philippe Co...
ADBIS
2006
Springer
135views Database» more  ADBIS 2006»
13 years 11 months ago
Interactive Discovery and Composition of Complex Web Services
Among the most important expected benefits of a global service oriented architecture leveraging web service standards is an increased level of automation in the discovery, composit...
Sergey A. Stupnikov, Leonid A. Kalinichenko, St&ea...