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JPDC
2007
84views more  JPDC 2007»
13 years 8 months ago
Performance of memory reclamation for lockless synchronization
Achieving high performance for concurrent applications on modern multiprocessors remains challenging. Many programmers avoid locking to improve performance, while others replace l...
Thomas E. Hart, Paul E. McKenney, Angela Demke Bro...
CHI
2002
ACM
14 years 9 months ago
A new technique for adjusting distraction moments in multitasking non-field usability tests
Evaluating errors that result from user interactions with incar applications, it has to be considered that the user is permanently involved with driving the car. Reproducing this ...
Björn Schuller, Frank Althoff, Gregor McGlaun...
ICDCS
2009
IEEE
14 years 5 months ago
Graduated QoS by Decomposing Bursts: Don't Let the Tail Wag Your Server
The growing popularity of hosted storage services and shared storage infrastructure in data centers is driving the recent interest in resource management and QoS in storage system...
Lanyue Lu, Peter J. Varman, Kshitij Doshi
DSD
2010
IEEE
172views Hardware» more  DSD 2010»
13 years 9 months ago
Adaptive Cache Memories for SMT Processors
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
Sonia López, Oscar Garnica, David H. Albone...
HIPEAC
2009
Springer
13 years 12 months ago
Accomodating Diversity in CMPs with Heterogeneous Frequencies
Shrinking process technologies and growing chip sizes have profound effects on process variation. This leads to Chip Multiprocessors (CMPs) where not all cores operate at maximum f...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee