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CAV
1998
Springer
175views Hardware» more  CAV 1998»
15 years 8 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
CONCUR
1998
Springer
15 years 8 months ago
Algebraic Techniques for Timed Systems
Performance evaluation is a central issue in the design of complex real-time systems. In this work, we propose an extension of socalled "Max-Plus" algebraic techniques to...
Albert Benveniste, Claude Jard, Stephane Gaubert
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
15 years 8 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
VISUALIZATION
1997
IEEE
15 years 8 months ago
Multiresolution compression and reconstruction
This paper presents a framework for multiresolution compression and geometric reconstruction of arbitrarily dimensioned data designed for distributed applications. Although being ...
Oliver G. Staadt, Markus H. Gross, Roger Weber
SIGGRAPH
1997
ACM
15 years 8 months ago
Interactive Boolean operations for conceptual design of 3-D solids
Interactive modeling of 3-D solids is an important and difficult problem in computer graphics. The Constructive Solid Geometry (CSG) modeling scheme is highly attractive for inte...
Ari Rappoport, Steven N. Spitz