85 search results - page 12 / 17 » Worst Cases and Lattice Reduction |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...
RTSS
2003
IEEE
14 years 23 days ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Memory size reduction and memory accesses optimization are crucial issues for embedded systems. In the context of affine programs, these two challenges are classically tackled by ...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...
JAIR
2008
13 years 7 months ago
2008
Inspired by AND/OR search spaces for graphical models recently introduced, we propose to augment Multi-Valued Decision Diagrams (MDD) with AND nodes, in order to capture function ...