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ISSS
1998
IEEE
103views Hardware» more  ISSS 1998»
13 years 11 months ago
False Path Analysis Based on a Hierarchical Control Representation
False path analysis is an activity with applications in a variety of computer science and engineering domains like for instance high-level synthesis, worst case execution time est...
Apostolos A. Kountouris, Christophe Wolinski
RTAS
2008
IEEE
14 years 1 months ago
Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
Jack Whitham, Neil C. Audsley
WORDS
2002
IEEE
14 years 10 days ago
Writing Temporally Predictable Code
The Worst-Case Execution-Time Analysis (WCET Analysis) of program code that is to be executed on modern processors is a highly complex task. First, it involves path analysis, to i...
Peter P. Puschner, Alan Burns
ECRTS
2004
IEEE
13 years 11 months ago
Static Determination of Probabilistic Execution Times
Most previous research done in probabilistic schedulability analysis assumes a known distribution of execution times for each task of a real-time application. This is however not ...
Laurent David, Isabelle Puaut
EMSOFT
2007
Springer
14 years 1 months ago
WCET estimation for executables in the presence of data caches
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
Rathijit Sen, Y. N. Srikant