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CASES
2006
ACM
13 years 11 months ago
An accurate and efficient simulation-based analysis for worst case interruption delay
This paper proposes an efficient method to analyze worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our...
Hiroshi Nakashima, Masahiro Konishi, Takashi Nakad...
RTAS
2006
IEEE
14 years 1 months ago
Estimating the Worst-Case Energy Consumption of Embedded Software
The evolution of battery technology is not being able to keep up with the increasing performance demand of mobile embedded systems. Therefore, battery life has become an important...
Ramkumar Jayaseelan, Tulika Mitra, Xianfeng Li
WORDS
2002
IEEE
14 years 9 days ago
A Static Timing Analysis Environment Using Java Architecture for Safety Critical Real-Time Systems
Certainly, in hard real-time systems, it is reasonable to argue that no hard real-time threads should behave in an unpredictable way and that schedulability should be guaranteed b...
Erik Yu-Shing Hu, Guillem Bernat, Andy J. Wellings
DATE
2010
IEEE
107views Hardware» more  DATE 2010»
14 years 15 days ago
Worst case delay analysis for memory interference in multicore systems
Abstract—Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access...
Rodolfo Pellizzoni, Andreas Schranzhofer, Jian-Jia...
RTAS
2008
IEEE
14 years 1 months ago
Bounding Worst-Case Response Time for Tasks with Non-Preemptive Regions
Real-time schedulability theory requires a priori knowledge of the worst-case execution time (WCET) of every task in the system. Fundamental to the calculation of WCET is a schedu...
Harini Ramaprasad, Frank Mueller