85 search results - page 12 / 17 » Wrong-path Instruction Prefetching |
POPL
1994
ACM
13 years 11 months ago
1994
ACM
Modern computer architectures increasingly depend on mechanisms that estimate future control flow decisions to increase performance. Mechanisms such as speculative execution and p...
PPSC
1997
13 years 8 months ago
1997
Sparse matrix-vector multiplication is an important kernel that often runs inefficiently on superscalar RISC processors. This paper describes techniques that increase instruction-...
ICS
2000
Tsinghua U.
13 years 11 months ago
2000
Tsinghua U.
As the performance gap between the CPU and main memory continues to grow, techniques to hide memory latency are essential to deliver a high performance computer system. Prefetchin...
ICPP
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper presents COBRA (Continuous Binary ReAdaptation), a runtime binary optimization framework, for multithreaded applications. It is currently implemented on Itanium 2 based...
MICRO
2003
IEEE
14 years 22 days ago
2003
IEEE
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...