Sciweavers

85 search results - page 9 / 17
» Wrong-path Instruction Prefetching
Sort
View
JILP
2000
109views more  JILP 2000»
13 years 7 months ago
Dynamic Register Renaming Through Virtual-Physical Registers
Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instructio...
Teresa Monreal, Antonio González, Mateo Val...
CAL
2005
13 years 7 months ago
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor
Previous research on runahead execution took it for granted as a prefetch-only technique. Even though the results of instructions independent of an L2 miss are correctly computed d...
Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt
MICRO
1997
IEEE
93views Hardware» more  MICRO 1997»
13 years 11 months ago
A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine
In this paper we investigate the behavior of data prefetching on an access decoupled machine and a superscalar machine. We assess if there are bene ts to using the decoupling para...
G. P. Jones, Nigel P. Topham
ARCS
2006
Springer
13 years 11 months ago
Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
Chen-Yong Cher, Il Park, T. N. Vijaykumar
MICRO
1995
IEEE
108views Hardware» more  MICRO 1995»
13 years 11 months ago
SPAID: software prefetching in pointer- and call-intensive environments
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
Mikko H. Lipasti, William J. Schmidt, Steven R. Ku...