Dynamic Register Renaming Through Virtual-Physical Registers

Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper present a novel dynamic register renaming scheme that delays the allocation of physical registers until a late stage in the pipeline. We show that it can provide important savings in number of physical registers so it can significantly shorter the register file access time. Delaying the allocation of physical registers requires some artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical registers, which are tags that do not require any storage location. The proposed renaming scheme shortens the average number of cycles that each physical register is allocated, and allows for an early execution of instructions since they can obtain a physical register for its destination earlier than with the conventional scheme. Earl...

• Type: Journal
• Year: 2000
• Where: JILP
• Authors: Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
• Keywords: File Access Time, JILP 2000, Physical Register, Register File Access