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SIGARCH
2008
97views more  SIGARCH 2008»
13 years 7 months ago
SP-NUCA: a cost effective dynamic non-uniform cache architecture
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
Javier Merino, Valentin Puente, Pablo Prieto, Jos&...
JUCS
2000
120views more  JUCS 2000»
13 years 7 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
INFOSCALE
2007
ACM
13 years 9 months ago
Load-balancing and caching for collection selection architectures
— To address the rapid growth of the Internet, modern Web search engines have to adopt distributed organizations, where the collection of indexed documents is partitioned among s...
Diego Puppin, Fabrizio Silvestri, Raffaele Perego,...
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
13 years 12 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
ASPDAC
2008
ACM
97views Hardware» more  ASPDAC 2008»
13 years 9 months ago
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt