Sciweavers

1000 search results - page 16 / 200
» Yield-Aware Cache Architectures
Sort
View
CODES
2010
IEEE
13 years 5 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu
TPDS
2008
134views more  TPDS 2008»
13 years 7 months ago
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
Ricardo Fernández Pascual, José M. G...
VLDB
1999
ACM
120views Database» more  VLDB 1999»
13 years 12 months ago
An Adaptive Hybrid Server Architecture for Client Caching ODBMSs
Kaladhar Voruganti, M. Tamer Özsu, Ronald C. ...
SC
1994
ACM
13 years 11 months ago
Tolerating node failures in cache only memory architectures
Alain Gefflaut, Christine Morin, Michel Banâ...
DATE
2004
IEEE
106views Hardware» more  DATE 2004»
13 years 11 months ago
A Self-Tuning Cache Architecture for Embedded Systems
Chuanjun Zhang, Frank Vahid, Roman L. Lysecky