Sciweavers

1000 search results - page 187 / 200
» Yield-Aware Cache Architectures
Sort
View
IPPS
2000
IEEE
14 years 2 days ago
Ordering Unstructured Meshes for Sparse Matrix Computations on Leading Parallel Systems
Abstract. Computer simulations of realistic applications usually require solving a set of non-linear partial di erential equations PDEs over a nite region. The process of obtaini...
Leonid Oliker, Xiaoye S. Li, Gerd Heber, Rupak Bis...
FCCM
1999
IEEE
122views VLSI» more  FCCM 1999»
14 years 1 hour ago
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
Andrew A. Chien, Jay H. Byun
AGENTS
1999
Springer
13 years 12 months ago
Planning and Resource Allocation for Hard Real-Time, Fault-Tolerant Plan Execution
We describe the interface between a real-time resource allocation system with an AI planner in order to create fault-tolerant plans that are guaranteed to execute in hard real-tim...
Ella M. Atkins, Tarek F. Abdelzaher, Kang G. Shin,...
CF
2009
ACM
14 years 2 months ago
Core monitors: monitoring performance in multicore processors
As we reach the limits of single-core computing, we are promised more and more cores in our systems. Modern architectures include many performance counters per core, but few or no...
Paul E. West, Yuval Peress, Gary S. Tyson, Sally A...
IPPS
2008
IEEE
14 years 2 months ago
Parallel IP lookup using multiple SRAM-based pipelines
Pipelined SRAM-based algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high throughput IP lookup. Multiple pipelines c...
Weirong Jiang, Viktor K. Prasanna