1000 search results - page 197 / 200 » Yield-Aware Cache Architectures |
CF
2009
ACM
14 years 2 months ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
SIGCOMM
2009
ACM
14 years 2 months ago
2009
ACM
The threat of commoditization poses a real challenge for service providers. While the end-to-end principle is often paraphrased as “dumb network, smart end-systems”, the origi...
ACSAC
2008
IEEE
14 years 2 months ago
2008
IEEE
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...
ISM
2008
IEEE
14 years 2 months ago
2008
IEEE
We present the architecture, user interface and prototype implementation of Fluid Voice, a proximity based mobile group communication system for opportunistic social exchanges. It...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...