Sciweavers

1000 search results - page 32 / 200
» Yield-Aware Cache Architectures
Sort
View
ICPP
1991
IEEE
13 years 11 months ago
Cache Coherence on a Slotted Ring
-- The Express Ring is a new architecture under investigation at the University of Southern California. Its main goal is to demonstrate that a slotted unidirectional ring with very...
Luiz André Barroso, Michel Dubois
CONEXT
2008
ACM
13 years 9 months ago
Incentive-compatible caching and peering in data-oriented networks
Several new, data-oriented internetworking architectures have been proposed recently. However, the practical deployability of such designs is an open question. In this paper, we c...
Jarno Rajahalme, Mikko Särelä, Pekka Nik...
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 2 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
ICON
2007
IEEE
14 years 2 months ago
A Cache Architecture for Counting Bloom Filters
— Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, e.g., u...
Mahmood Ahmadi, Stephan Wong
ICS
2009
Tsinghua U.
14 years 2 months ago
Dynamic cache clustering for chip multiprocessors
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is compri...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem