1000 search results - page 51 / 200 » Yield-Aware Cache Architectures |
GLVLSI
2011
IEEE
12 years 11 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
ICS
1999
Tsinghua U.
14 years 1 days ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
TVCG
2010
13 years 2 months ago
2010
Abstract--One important bottleneck when visualizing large data sets is the data transfer between processor and memory. Cacheaware (CA) and cache-oblivious (CO) algorithms take into...
ICPP
1990
IEEE
13 years 12 months ago
1990
IEEE
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...